Disclaimer: This post is for informational purposes. PCI Express, PCI-SIG, and the PCIe Base Specification are trademarks of PCI-SIG. Always refer to the official specification documents for design guidance.
PCIe 6.0 builds upon the ASPM (Active State Power Management) L1 sub-states. The specification optimizes the entry and exit times for low-power states. Because PAM-4 signaling consumes more power per logic gate than NRZ (due to the complexity of the DSP and FEC), the ability to enter deep sleep states quickly during idle periods is crucial for energy efficiency. pci express base specification revision 6.0 pdf